Practical RTL subset score in the current coverage report dated 2026-04-12.
Commercial VHDL Translation
SystemVerilog migration for practical VHDL codebases.
vhdl2sv is a local desktop and CLI translator built for engineers moving supported VHDL designs into SystemVerilog. It focuses on a proven RTL-oriented subset, preserves source context, and is backed by a growing regression and ModelSim-based validation flow.
Current documented automated test pass count for the repository suite.
Current direct-translation benchmark result cited in the coverage report.
The full IEEE 1076-2008 language is not yet complete. The product is positioned around the supported practical subset documented in the repository today.
Product Positioning
Built for FPGA, ASIC, and EDA teams that need migration throughput without pretending every language corner is solved.
RTL-focused translation
The documented strong path covers common entities, architectures, packages, declarations, processes, assignments, instantiations, and generate structures used in practical projects.
Local by default
The desktop application and CLI are intended for local project processing. The current product does not rely on uploading HDL source to a hosted translation service for its normal local use path.
Commercially grounded
Perpetual licensing, email-based support, and manual quote handling fit teams that want a direct tool purchase instead of a hosted subscription dependency.
Key Features
What the first release site is comfortable claiming.
Preserves engineering context
Repository docs describe a strong emphasis on preserving comments, spacing, and source spans where the supported pipeline can carry them through.
Coverage that is documented, not guessed
The public position tracks the current coverage report: strong on a practical subset, incomplete for the full standard, and honest about remaining gaps.
Validation flow already matters
The repo cites a growing regression suite, a ModelSim-based flow, and benchmark evidence instead of relying only on hand-picked examples.
Typical Uses
Legacy IP
Reduce manual rewrite time when moving older VHDL blocks into a SystemVerilog-centered codebase.
Mixed-language cleanup
Inspect translation output, then continue hand-tuning only where the project actually needs it.
Vendor and partner intake
Use translation as an engineering accelerant when assessing incoming VHDL collateral or integration risk.
Commercial Policy Snapshot
Launch pricing is simple: perpetual licenses, direct support, and quotes for larger teams.
Single user
EUR 149.99
Suggested public launch price, VAT included where required.
- Perpetual desktop license
- Bug-fix and security-fix updates for the supported purchased release line
- Direct email support for product issues and mistranslations
Business
From EUR 590 / seat
Suggested company starting point, typically quoted exclusive of VAT.
- Per-seat commercial licensing
- Manual quote and invoicing workflow
- Scope, support, and upgrade terms confirmed in the commercial record
Team / enterprise
Custom quote
For larger seat counts, floating setups, or tailored support expectations.
- Custom commercial structure
- Quote-based licensing conversation
- Commercial and technical fit review
The current business docs recommend manual sales contact during the initial launch phase instead of immediate self-serve checkout.
Contact and Legal
Public-facing terms are published with the site and routed to dedicated domain mailboxes.
The footer links expose the current EULA, terms of sale, privacy notice, support policy, copyright notice, and third-party notices. Commercial, support, legal, and general contact routes each have a dedicated mailbox.